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Jtag/Ejtag

The JTAG interface, collectively known as a Test Access Port(TAP), uses the following signals to support the operation of boundary scan.

1. TCK (Test Clock) – this signal synchronizes the internal state machine operations.
2. TMS (Test Mode Select) – this signal is sampled at the rising edge of TCK to determine the next state.
3. TDI (Test Data In) – this signal represents the data shifted into the device's test or programming logic. It is sampled at the rising edge of TCK when the internal state machine is in the correct state.
4. TDO (Test Data Out) – this signal represents the data shifted out of the device's test or programming logic and is valid on the falling edge of TCK when the internal state machine is in the correct state.
5. TRST (Test Reset) – this is an optional pin which, when available, can reset the TAP controller's state machine.

The functionality usually offered by JTAG is Debug Access and Boundary Scan:

1. Sebug Access is used by debugger tools to access the internals of a chip making its resources and functionality available and modifiable, e.g. registers, memories and the system state.
2. Boundary Scan is used by hardware test tools to test the physical connection of a device, e.g. on a PCB. Although this is usually not the task of a debugger tool the TRACE32 debugger offers mechanisms to access the JTAG TAP in a generic way, e.g. to perform boundary scan using a PRACTICE script or a custom application.