MIPS | [[http://logos.cs.uic.edu/366/notes/mips%20quick%20tutorial.htm#RegisterDescription|MIPS quick Tutoria]] | {{:mywiki:hw:mips:pcspim-tutorial.pdf|}} | [[TLB]] | [[Barrier_Fence|Barrier/Pipeline Hazards/Align]] | [[LinkScript|Link Script Guide]] | [[cache]] | | [[MipsSimulator]] | {{:mywiki:hw:mips:cs50-asm.pdf|MIPS ASM Programming}} | {{:mywiki:hw:mips:mips-iv.pdf| MIPS IV Instruction Set}} | {{:mywiki:hw:mips:mips_exception.pdf| MIPS exception}} | {{:mywiki:hw:mips:mips_vol3.pdf| MIPS Vol3}} | ====== Common Instruction ====== For details, refer to below documents: * {{:mywiki:hw:mips:mips-iv.pdf| MIPS IV Instruction Set}} * [[http://en.wikipedia.org/wiki/MIPS_instruction_set#MIPS_assembly_language]] ===== Normal CPU Load/Store Instructions ===== | LB | Load Byte | | LBU | Load Byte Unsigned | | SB Store | Byte | | LH | Load Halfword | | LHU | Load Halfword Unsigned | | SH | Store Halfword | | LW | Load Word | | LWU | Load Word Unsigned | | SW | Store Word | | LD | Load Doubleword | | SD | Store Doubleword | ===== Unaligned CPU Load/Store Instructions ===== * MIPS permits LWL and LWR instructions targeting the same destination register to be executed sequentially. * Store instructions select the correct bytes from a source register and update only those bytes in an aligned memory word (or doubleword) | LWL | Load Word Left | | LWR | Load Word Right | | SWL | Store Word Left | | SWR | Store Word Right | | LDL | Load Doubleword Left | | LDR | Load Doubleword Right | | SDL | Store Doubleword Left | | SDR | Store Doubleword Right | ===== Atomic Update CPU Load/Store Instructions ===== | LL | Load Linked Word | | SC | Store Conditional Word | | LLD | Load Linked Doubleword | | SCD | Store Conditional Doubleword | ===== Shift Instructions ===== ROTR Rotate Word Right SLL Shift Word Left Logical SLLV hift Word Left Logical Variable SRL Shift Word Right Logical SRA Shift Word Right Arithmetic ROTRV Rotate Word Right Variable SLLV Shift Word Left Logical Variable SRLV Shift Word Right Logical Variable SRAV Shift Word Right Arithmetic Variable DSLL Doubleword Shift Left Logical DSRL Doubleword Shift Right Logical DSRA Doubleword Shift Right Arithmetic DSLL32 Doubleword Shift Left Logical + 32 DSRL32 Doubleword Shift Right Logical + 32 DSRA32 Doubleword Shift Right Arithmetic + 32 DSLLV Doubleword Shift Left Logical Variable DSRLV Doubleword Shift Right Logical Variable DSRAV Doubleword Shift Right Arithmetic Variable ===== PC-Relative Conditional Branch Instructions Comparing 2 Register ===== EQ Branch on Equal MIPS BNE Branch on Not Equal BLEZ Branch on Less Than or Equal to Zero BGTZ Branch on Greater Than Zero BEQL Branch on Equal Likely BNEL Branch on Not Equal Likely BLEZL Branch on Less Than or Equal to Zero Likely BGTZL Branch on Greater Than Zero Likely ===== PC-Relative Conditional Branch Instructions Comparing Against Zero ===== BLTZ Branch on Less Than Zero BGEZ Branch on Greater Than or Equal to Zero BLTZAL Branch on Less Than Zero and Link BGEZAL Branch on Greater Than or Equal to Zero and Link BLTZL Branch on Less Than Zero Likely BGEZL Branch on Greater Than or Equal to Zero Likely BLTZALL Branch on Less Than Zero and Link Likely BGEZALL Branch on Greater Than or Equal to Zero and Link Likely ===== Serialization Instructions ===== | sync | Loads and stores executed before the SYNC are completed before loads and stores after the SYNC can start. | ===== Prefetch ===== here are two prefetch advisory instructions; one with register+offset addressing and the other with register+register addressing. These instructions advise that memory is likely to be used in a particular way in the near future and should be CPU Instruction Set MIPS IV Instruction Set. Rev 3.2 -11 prefetched into the cache. The PREFX instruction using register+register addressing mode is coded in the FPU opcode space along with the other operations using register+register addressing. Prefetch Using Register + Offset Address Mode | PREF | Prefetch Indexed | Prefetch Using Register + Register Address Mode | PREFX | Prefetch Indexed | ====== MIPS C and Assembly ====== ===== If/then/else ===== | C Conditional Operator | MIPS Assembly Instruction | | a==b | beq $t0,$t1,then | | a != b | bne $t0, $t1, then | | a < b | blt $t0, $t1, then | | a > b | bgt $t0, $t1, then | | a<=b | ble $t0,$t1,then | | a>=b | bge $t0,$t1,then | | a == 0 | beqz $t0, then | ===== Loop ===== | C Loop | Assembly loop | | int i; for( i=0;i<10;i++ ) { loop body } int i=0; while (i<10){ loop body i++; } | li $t0, 10 #t0 is a constant 10 li $t1, 0 #t1 is our counter (i) loop: beq $t1, $t0, end #if t1 == 10 we are done loop body addi $t1, $t1, 1 #add 1 to t1 j loop #jump back to the top end: | ===== strlen example of assembly ===== strlen: li $t0, 0 #initialize the count to zero loop: lbu $t1, 0($a0) # load the next character into t1 beqz $t1, exit # check for the null character addi $a0, $a0, 1 # increment the string pointer addi $t0, $t0, 1 # increment the count j loop # return to the top of the loop exit: =====max example of assembly ===== max: lw $t0, 0($a0) # load the first array value into t0 li $t1, 1 # initialize the counter to one loop: beq $t1, $a1, exit #exit if we reach the end of the array addi $a0, $a0, 4 #increment the pointer by one word addi $t1, $t1, 1 #increment the loop counter lw $t2, 0($a0) #store the next array value into t2 ble $t2, $t0, end_if move $t0, $t2 #found a new maximum, store it in t0 end_if: j loop #repeat the loop exit: ====== Function call ====== |jal | jump and link | saves the return address (the address of the next instruction, ie $PC + 4) in the dedicated register $ra, before jumping to the function | | jr | jump and return | To transfer control back to the caller, the function just has to jump to the address that was stored in $ra | ===== Register Convention ===== * Up to four function arguments can be "passed" by placing them in argument registers $a0-$a3 before calling function via jal * A function can "return" up to two values by placing them in registers $v0-$v1 before returning via jr The caller is responsible for saving/restoring any of the following caller-­saved registers: * $t0-$t9 * $a0-$a3 * $v0-$v1 The callee is responsible for saving/restoring any of the following callee-­saved registers: * $s0-$s7 $ra is special; it is "used" by jal. It is saved by a callee who is also a caller. ===== Stack frame usage ===== | $sp | stack pointer points to the top of the stack. | | $fp | frame pointer ($fp) points to the start of the stack frame and does not move for the duration of the subroutine call. This points to the base of the stack frame, and the parameters that are passed in to the subroutine remain at a constant spot relative to the frame pointer | ==== Push registers $t1 and $t2 onto the stack ==== sub $sp, $sp, 8 sw $t1, 4($sp) sw $t2, 0($sp) An equivalent sequence is: sw $t1, -4($sp) sw $t2, -8($sp) sub $sp, $sp, 8 ==== Access value in stack frame ==== lw $s0, 4($sp) ==== Pop $t1/$t2 from stack frame ==== addi $sp, $sp, 8 ===== function call example ===== _start: #save registers sw $t1, -4($sp) sw $t2, -8($sp) sw $v1, -12($sp) sw $v2, -16($sp) sub $sp, $sp, 16 #set function parameters li $a1, 4 #set function parameters #call function/subroutine jal func1 #restore saved registers lw $t1, -4($sp) lw $t2, -8($sp) lw $v1, -12($sp) lw $v2, -16($sp) addi $sp, $sp, 16 #use return value $v1/v2 .... func1: .... #prepare returned value in $v1/$v2 sw $v1, 10 sw $v1, 100 #return to the caller jr $ra